Apple is reportedly testing a new 3D chip stacking technology called System Integration Chip (SoIC), which is expected to be launched in the period between 2025 and 2026. The information was shared by a user on the social network Naver, who revealed that TSMC is making efforts to enhance the production capacity of CoWoS packaging technology and is also exploring solutions for the next-generation SoIC solution. The SoIC chips will be produced in small-scale trials initially and are expected to be officially mass-produced by 2025.
SoIC is an industry-first high-density 3D small-chip stacking technology that allows for the integration of chips with different sizes, functions, and nodes heterogeneously through Chip on Wafer (CoW) packaging technology. TSMC’s Nanjing Plant (AP6) is responsible for SoIC’s mass production. Compared to 2.5D solutions, SoIC has a higher collision density, which not only reduces overall power consumption but also increases density and transfer speed, resulting in higher memory bandwidth.
Another advantage of SoIC packaging is its ability to reduce the size of semiconductors, enabling Apple to produce smaller chips and save space. Additionally, the technology helps reduce the cost of integrated circuit boards, which can save Apple a significant amount of money. Although it is unclear which product lines will be equipped with the new chip, sources suggest that the chip will likely be pre-ordered for use in MacBooks.
